AsteRISC

Overview

AsteRISC is a flexible multi-cycle RISC-V core designed for design space exploration.

It is written in platform-independent SystemVerilog and targets both FPGAs and ASIC technologies.

Supported RISC-V extensions: RV32[I/E][M][C][Zicsr]

Key Features

• Architectural flexibility for generating a wide array of microarchitectures.

• Designed to cater to diverse performance requirements and application scenarios.

• Suited for both FPGA and physical (ASIC) implementation.

Contents

User Guide

• Installation
  • Get AsteRISC
    • Step 1: Clone the repository
  • Install EDA tools
  • Install Asterism
    • Step 1: Install Python 3.6+ and make
    • Step 2: Install Python requirements
      • Option #1: Using pipx (recommended)
      • Option #2: Using pip
• Quick start
  • Compare configurations
    • Step 1: Run benchmarks
    • Step 2: Run the fmax synthesis
    • Step 3: Visualize and explore the results
  • Run simulations

Documentation

• Principle
• Processor Stages
  • Fetch Stage
  • Decoder Module
  • Register File
  • Execution Stage
  • Memory Access Stage
  • Write-Back Stage