AsteRISC

Overview

AsteRISC is a flexible multi-cycle RISC-V core designed for design space exploration.

It is written in platform-independent SystemVerilog and targets both FPGAs and ASIC technologies.

Supported RISC-V extensions: RV32[I/E][M][C][Zicsr]

Key Features

• Architectural flexibility for generating a wide array of microarchitectures.

• Designed to cater to diverse performance requirements and application scenarios.

• Suited for both FPGA and physical (ASIC) implementation.

• Uses Odatix to help you find the configuration that best suits your application needs.

Contents

User Guide

• Installation
  • Get AsteRISC
    • Step 1: Install git
    • Step 2: Clone the repository
  • Install the environment
    • Step 1: Install Python 3.6+ and make
    • Step 2: Install the Odatix based virtual environment
  • Install EDA tools
• Quick start
  • Compare configurations
    • Step 1: Run benchmarks
    • Step 2: Run the fmax synthesis
    • Step 3: Visualize and explore the results
  • Run simulations
• Software
  • Run your own code
    • Step 1: Install the RISC-V toolchain
    • Step 2: Setup your environment
    • Step 3: Compile examples
    • Step 4: Edit the default program
    • Step 5: Run a simulation of your program
    • Step 6: Add new programs

Documentation

• Principle
• Processor Stages
  • Fetch Stage
  • Decoder Module
  • Register File
  • Execution Stage
  • Memory Access Stage
  • Write-Back Stage