Processor Stages
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This section provides a detailed overview of the various stages involved in the processor's operation.

Fetch Stage
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The fetch stage is the initial phase, where the instruction to be executed is fetched from memory.
This stage involves the program counter (PC), which holds the address of the next instruction to be executed.
The instruction is then read from the memory and placed into the instruction register, ready for the decode stage.

Decoder Module
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In the decode stage, the fetched instruction is interpreted.
The SystemVerilog `casez` construct is utilized to easily compare opcodes regardless of their positions.
Control signals employ enums to enhance readability and clarity, allowing for straightforward modification and addition of control signals for each instruction.

Register File
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The register file in the processor core offers multiple implementations to cater to various requirements.
The first implementation uses flip-flops, providing synchronous writes and asynchronous reads, potentially reducing the number of cycles per instruction at the cost of increased hardware area.
Another implementation uses double-port SRAM, where both reads and writes are synchronous, offering better density and suitable for minimizing hardware area.
A third approach uses single-port SRAM, requiring up two cycles to fetch register values depending on the instruction, but ensuring compatibility with a wider range of technologies.

Execution Stage
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The execution stage encompasses the Arithmetic Logic Unit (ALU) responsible for performing arithmetic and logical operations on data.
AsteRISC supports the M extension of the RISC-V architecture by including an optional multiplier/divider.

Memory Access Stage
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The memory access stage handles memory read and write operations.
This stage interacts with the memory subsystem through a data bus, ensuring data read from or written to memory is properly aligned based on the data size.
The module performs sign and zero extension on data read from memory to retain its correct value and sign.

Write-Back Stage
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The write-back stage is the final stage in the processor core, where the results of computations are written back to the register file.
This stage updates the register file with data generated by the execution stage, memory access stage, or co-processors.
An interface for co-processors enables parallel execution of calculations, enhancing flexibility and parallel processing capabilities.